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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
Features
Integrated I/Q demodulator with IF VGA Amplifier Operating IF Frequency 50-1000 MHz (3dB IF BW of 500MHz driven from Rs=200ohms) Demodulation Bandwidth 60MHz Linear-in-dB AGC Range 45dB Third Order Intercept IIP3 +26 dBm @ min gain (FIF=450MHz) IIP3 -7 dBm @ max gain (FIF=450MHz) Quadrature Demodulation Accuracy o Phase Accuracy 0.6 RMS Amplitude Balance 0.3 dB Noise Figure 12.5dB @ max gain (FIF=500MHz) LO Input -10 dBm Single Supply 2.7-5.5V Power down mode Compact 28-pin TSSOP package
50-1000 MHz Quadrature Demodulator
AD8348
Functional Block Diagram
Applications
QAM/QPSK Demodulator W-CDMA/CDMA/GSM/NADC Wireless Local Loop LMDS/MMDS
General Description The AD8348 is a broadband quadrature demodulator with an integrated intermediate frequency (IF) variable-gain amplifier (VGA) and integrated baseband amplifiers. It is suitable for use in communications receivers, performing quadrature demodulation from IF directly to baseband frequencies. The baseband amplifiers have been designed to directly interface with dual channel A-to-D converters such as the AD9201, AD9283, and AD9218 for digitizing and post-processing. The IF input signal is fed into two Gilbert-cell mixers through an X-AMP VGA. The IF VGA provides 45dB of gain control. A precision gain-control circuit sets a linear-in-dB gain characteristic for the VGA and provides temperature compensation. The LO quadrature phase splitter employs a divide-by-two frequency divider to achieve high quadrature accuracy and amplitude balance over the entire operating frequency range. Optionally, the IF VGA can be disabled and bypassed. In this mode, the IF signal is applied directly to the quadrature mixer inputs via pins MXIP and MXIN.
Separate I & Q-channel baseband amplifiers follow the baseband outputs of the mixers. The DC common-mode voltage level at the baseband outputs is set by the voltage applied to the VCMO pin. Typically VCMO is connected to the internal VREF voltage but it can also be connected to an external voltage. This flexibility allows the user to maximize the input dynamic range to the A-to-D converter. Connecting a bypass capacitor at each offset compensation input (IOFS & QOFS) nulls DC offsets produced in the mixer. Offset compensation can be overridden by applying an external voltage at the offset compensation inputs. The mixers' outputs are brought off-chip for optional filtering before final amplification. Inserting a channel selection filter before each baseband amplifier increases the baseband amplifiers' signal handling range by reducing the amplitude of high-level, out-of-channel interferers before the baseband signal is fed into the baseband amplifiers. The single-ended mixer output is amplified and converted to a differential signal for driving ADCs.
Rev. PrF
2/11/03
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 World Wide Web Site: http://www.analog.com (c)Analog Devices, Inc., 2003
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PRELIMINARY TECHNICAL DATA
(V = AD8348-SPECIFICATIONS unless5V; T =25 C; F =500MHz; F otherwise noted)
S A LO IF
=501MHz; Plo=-10dBm, Rs(LO)= 50 , Rs(IF)=200,
Parameter GENERAL LO Frequency Range IF Frequency Range Baseband bandwidth LO Input Level LO Input Impedance VGIN Input Level REFERENCE VOLTAGE VREF
Condition
External input must be 2x LO frequency
Min 100 50
Typ
Max 2000 1000 60 0
Units MHz MHz MHz dBm ||pF V V
50 source, LOIP/LOIN terminated to 50 Measured differentially across LOIP/LOIN
-10 320||1pF 0.2 1
1.2
POWER SUPPLIES Voltage Current Active Current Standby
ENBL=5V ENBL=0
2.7 48 65
5.5
V mA uA
-2-
Rev. PrF
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PRELIMINARY TECHNICAL DATA
Parameter IF FRONT-END WITH VGA Zin Variable Gain Range Linear-in-dB error Maximum Conversion Gain Minimum Conversion Gain Conversion Gain 3 dB Bandwidth IF Gain Flatness 2nd Order Input Intercept(IIP2)
FIF=50MHz-500MHz IF1=455MHz, IF2=456MHz -10 dBm each tone from 200 source VGIN=1.2V (min gain) VGIN=0.3 to 1.1V VGIN=0.2V (max gain) VGIN=1.2V (min gain)
AD8348
Units
Condition
IFIP/IFIN to IMXO/VREF, QMXO/ VREF ENVG=5V
Min
Typ
Max
150||1pF
190||1pF 45 +/-1 33 -14
230||1pF ||pF dB dB dB dB 500 MHz dB p-p dBm
3 55
3rd Order Input Intercept(IIP3)
IF1=455MHz, IF2=456MHz -10 dBm each tone from 200 source VGIN=1.2V (min gain)
26
dBm
2nd Order Input Intercept(IIP2)
IF1=455MHz, IF2=456MHz -42 dBm each tone from 200 source VGIN=0.2V (max gain)
20
dBm
3rd Order Input Intercept(IIP3)
IF1=455MHz, IF2=456MHz -42 dBm each tone from 200 source VGIN=0.2V (max gain)
-7
dBm
1dB Input compression point Noise Figure
VGIN=0.2V (max gain) VGIN=0.2V (max gain) From 200 source Double sideband measurement FIF=50MHz FIF=500MHz
-23 10 12.5 -125 10 TBD 60 0.6 0.3 40 2.5
dBm dB
Input LO Leakage Output LO Leakage Demodulation Bandwidth Quadrature Phase Error I/Q Amplitude Imbalance Mixer Output Impedance Mixer Peak output current
Measured at IFIP,IFIN Measured at IMXO/QMXO (LO=50MHz) Full-power bandwidth (IIP3 drops 3dB) Small-signal 3dB bandwidth LO=1GHz (LOIP/LOIN 2GHz, singleended)
dBm mVp-p MHz MHz deg RMS dB mA
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AD8348
Parameter
PRELIMINARY TECHNICAL DATA
Condition
from MXIP,MXIN to IMXO/QMXO ENVG=0V
Min
Typ
Max
Units
IF FRONT-END WITHOUT VGA Zin Conversion Gain Conversion Gain 3 dB Bandwidth IF Gain Flatness 2nd Order Input Intercept(IIP2) 3rd Order Input Intercept(IIP3) 1dB Input compression point Noise Figure Input LO Leakage Output LO Leakage Demodulation Bandwidth Quadrature Phase Error I/Q Amplitude Imbalance Capacitive load Resistive load Peak output current BASEBAND AMPLIFIER Gain Output Swing Input referred Noise Voltage Bandwidth Output DC differential offset Output Common-mode offset Group Delay Flatness 3rd Order Intermod. Distortion Capacitive load drive capability Resistive load
Measured differentially across MXIP/ MXIN
150||0.5pF 200 || 0.5pF 240||0.5pF ||Pf 12 TBD dB MHz dB p-p dBm dBm dBm dB dBm mVp-p MHz MHz deg RMS dB pF mA
FIF=50MHz-1GHz IF1=455MHz, IF2=456MHz -32 dBm each tone from 200 source IF1=455MHz, IF2=456MHz -32 dBm each tone from 200 source VGIN=0.2V (max gain) VGIN=0.2V (max gain) From 200 source Double sideband measurement Measured at MXIP/MXIN Measured at IMXO/QMXO Full-power bandwidth (IIP3 drops 3dB) Small-signal 3dB bandwidth, 10pF load LO=1GHz (LOIP/LOIN 2GHz, single- ended input)
TBD TBD TBD -23 TBD -120 10 TBD 60 0.6 0.3
shunt from IMXO,QMXO to VCMO shunt from IMXO,QMXO to VCMO
0 200 2.5
10
from IAIN to IOPP/IOPN & QAIN to QOPP/QOPN
20
differential
dB Vpp diff nV/rtHz MHz mV mV ns pp dBc pF ohm
2 8 60 +/-30 +/-15
10pF differential load Corrected using 500pF capacitor on IOFS,QOFS
0.1-30MHz Fin1=5MHz Fin2=6MHz Vin1=Vin2=50mVp-p Differential across IOPP/IOPN, QOPP/QOPN Differential across IOPP/IOPN, QOPP/QOPN
0.3 -71 10 2k 1
Peak output current Specifications subject to change without notice.
mA
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PRELIMINARY TECHNICAL DATA
AD8348
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS* Supply Voltage VPS1, VPS2, VPS3...............5.5V LO & RF Input Power ........................TBD dBm Internal Power Dissipation ..........................TBD JA ..............................................TBD C/W Maximum Junction Temperature ...........+TBD C Operating Temperature Range ....-40 C to +85 C Storage Temperature Range ......-65 C to +150 C Lead Temperature (Soldering 60 sec)......+TBD C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
C U IO AT N
E S D ( e le c t r o s t a t i c d is c h a r g e ) s e n s it i v e d e v ice. E lectrostatic cha rg es as hig h as 4000 V readily a c c u m u la t e o n t h e h u m a n b o d y a n d t e s t e q uipm ent a nd c an discharg e witho ut detec tion. Altho u g h t h e A D 8 3 4 8 f e a t u r e s p r o p r ie t a r y E S D p r o t e ction circuitry, pe rm anent da m ag e m ay o ccur on d e v ic e s s u b j e c t e d t o h ig h e n e r g y [ > 2 5 0 V H B M ] electrostatic discharg es. T herefore, proper E SD p r e c a u t i o n s a r e r e c o m m e n d e d t o a v o id p e r form ance d eg rad atio n or loss of functionality.
W N A G ESD SENSITIVE DEVICE
ORDERING GUIDE
Model AD8348XXX AD8348-EVAL Temp. Range -34 C to +85 C Package Description 28-Lead TSSOP Thin Shrink Small Outline Package Evaluation Board Package Option RU-28
Rev. PrF
2/11/03
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PRELIMINARY TECHNICAL DATA
AD8348
Pin 1,28 2, 12, 20 3,4, 25, 26 5 6 Name LOIP,LOIN VPS1, VPS2, VPS3 IOPN,IOPP, QOPP, QOPN VCMO IAIN
PIN FUNCTION DESCRIPTIONS
Description LO Input. For optimum performance, these inputs should be driven differentially. Typical input drive level is equal to -10 dBm. To obtain a broadband 50 input impedance, connect a 60.4 shunt resistor between LOIP and LOIN. Positive Supply for LO, IF, and Biasing & Baseband sections respectively. Each of these pins should be decoupled with 0.1 uF and 100 pF capacitors. I- and Q-channel differential baseband outputs. Typical output swing is equal to 2Vpp differential. The DC common-mode voltage level on these pins is set by the voltage on VCMO. Baseband DC common-mode voltage. The voltage applied to this pin sets the DC common-mode levels for all the baseband outputs and inputs (IMXO, QMXO, IOPP, IOPN, QOPP, QOPN, IAIN and QAIN). This pin can either be connected to VREF or to a reference voltage from another device, such as an ADC). I-channel baseband amplifier input. The single-ended signal on this pin is referenced to VCMO and should have a DC bias equal to the DC voltage on the VCMO pin. If IAIN is DC-coupled to IMXO, biasing will be provided by IMXO. If an AC-coupled filter is placed between IMXO and IAIN, this pin can be biased from VREF through a 1 k resistor. The gain from IAIN to the differential outputs IOPN/IOPP is 20 dB. Ground for Biasing and Baseband sections. I- and Q-channel mixer baseband outputs. These are low impedance (40 Ohms) outputs whose bias level is set by the voltage on the VCMO pin. These pins are typically connected to IAIN and QAIN respectively, either directly or through a filter. These outputs can drive a maximum current of 2.5 mA IF Section Ground IF Input. IFIN should be AC-coupled to ground. The single-ended IF input signal should be AC-coupled into IFIP. The nominal differential impedance of these pins is 200 Ohms. For a broadband 50 input impedance, a minimum loss L-pad should be used. Rseries=174 Ohms, Rshunt=57.6 Ohms. I- and Q-channel offset nulling inputs. DC offsets on the I-channel mixer output (IMXO) can be nulled by connecting a 0.1 uF capacitor from IOFS to ground. Driving IOFS with a fixed voltage (typically from a DAC) can extended the operating frequency range to include DC by nulling out the offset at the baseband outputs. Reference Voltage Output. This output voltage (1V) is the main bias level for the device and can be used to externally bias the inputs and outputs of the baseband amplifiers. Chip Enable Input. Active high. Threshold is equal to +Vs/2. Gain Control Input. The voltage on this pin controls the gain on the RF VGA. The gain control voltage range is from 0.2 V to 1.2 V and corresponds to a conversion gain range from +25 dB to -18 dB. This is the gain to the output of the mixers (i.e. QMXO and IMXO). There is an additional 20 dB of gain in the final baseband amplifiers (IAIN to IOPP/IOPN and QAIN to QOPP/QOPN). Note that the gain control function has a negative sense (i.e. increasing voltage decreases gain). Auxiliary mixer inputs. If ENVG is low then the IFIP, IFIN inputs are disabled and MXIP, MXIN are enabled, allowing the VGA to be bypassed. This is a fully differential input which should be AC coupled to the signal source. Q-channel baseband amplifier input. The single-ended signal on this pin is referenced to VCMO and should have a DC bias equal to the DC voltage on the VCMO pin. If QAIN is DC-coupled to QMXO, biasing will be provided by QMXO. If an AC-coupled filter is placed between QMXO and QAIN, this pin can be biased from VREF through a 1 k resistor. The gain from QAIN to the differential outputs QOPN/QOPP is 20 dB. Active high VGA enable. When ENVG is high, IFIP, IFIN inputs are enabled and MXIP, MXIN inputs are disabled. When ENVG is low, MXIP, MXIN inputs are enabled and IFIP, IFIN inputs are disabled. LO Section Ground Equiv. Cir.
7,22 8,21 9 10, 11 13, 16 14 15 17
COM3 IMXO, QMXO COM2 IFIN,IFIP IOFS, QOFS VREF ENBL VGIN
18, 19 23
MXIP, MXIN QAIN
24 27
ENVG COM1
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PRELIMINARY TECHNICAL DATA
Theory of operation
VGA The VGA is implemented using the patented X-AMP architecture. The single-ended IF signal is attenuated in eight discrete 6-dB steps by a passive R-2R ladder. Each discrete attenuated version of the IF signal is applied to the input of a transconductance stage. The current outputs of all transconductance stages are summed together and drive a resistive load at the output of the VGA. Gain control is achieved by smoothly turning on and off the relevant transconductance stages with a temperature-compenstated interpolation circuit. This scheme allows the gain to continuously varied over a 48dB range with linear-in-dB gain control. This configuration also keeps the relative dynamic range constant (e.g. IIP3-NF in dB) over gain setting. The absolute intermodulation intercepts and noise figure, however, vary directly with gain. The analog voltage VGIN sets the gain. VGIN=0V is the maximum gain setting, and VGIN=1.2V is the minimum voltage gain setting. Downconversion mixers The output of the VGA drives two (I & Q) double-balanced Gilbert-cell down-conversion mixers. Alternatively, the VGA can be disabled by driving the ENVG pin low and the mixers can be driven directly externally via the MXIP, MXIN port. At the input of the mixer, a degenerated differential pair performs linear voltage-to-current conversion. The differential output current feeds into the mixer core where it is downconverter by the mixing action of the Gilbert cell. The phase splitter provides quadrature LO signals which drive the LO ports of the in- phase and quadrature mixers. Buffers at the output of each mixer drive pins IMXO and QMXO respectively. These linear, low-output impedance buffers drive 40ohm temperature-stable, passive resistors in series with each of the output pins (IMXO, QMXO). This 40ohms should be considered when calculating the reverse termination if an external filter is inserted between IMXO(QMXO) and IAIN(QAIN). The DC output level of the buffer is set by the VCMO pin. This can be set externally or connected to the on-chip 1.0V reference VREF. Phase splitter Quadrature generation is achieved using a divide-by-two frequency divider. Unlike a poly-phase filter which achieves quadrature over a limited frequency range, the divide-by-two approach maintains quadrature over a broad frequency range and does not attenuate the LO. The user, however, must provide an external reference XLO which is twice the frequency of the desired LO frequency. XLO drives the clock inputs of two flip-flops which divide down the frequency by a factor of two. The outputs of the two flip-flops are one half-
AD8348
period of XLO out of phase. Equivalently, the outputs are one quarter-period (90 degrees) of the desired LO frequency out of phase. Because the transitions on XLO define the phase difference at the outputs, deviation from 50% duty cycle translates directly to quadrature phase errors. Baseband amplifiers Two (I &Q) fixed-gain (20dB), single-ended to differential amplifers are provided to amplify the demodulated signal after off-chip filtering. The amplifiers use voltage feedback to linearize the gain over the demolation bandwidth. These amplifiers can be used to maximize the dynamic range at the input of an ADC following the AD8348. The input to the baseband amplifiers IAIN (QAIN) feeds into the base of a bipolar transistor with an input impedance of roughly 100kohm. The baseband amplifiers sense the singleended difference between IAIN (QAIN) and VCMO. IAIN can be DC biased by terminating with a shunt resistor to VCMO, such as when an external filter is inserted between IMXO (QMXO) and IAIN (QAIN). Alternatively, any DC connection to IMXO (QXMO) can provide appropriate bias via the offset-nulling loop. Bias The global bias for the chip is controlled by a master biasing cell that can be disabled using the ENBL pin. If the ENBL is held low, the entire chip will power down to a low-power sleep mode typically consuming 60uA at 5V. Baseband offset cancellation A low output current integrator senses the output voltage offset at IOPP,IOPN (QOPP,QOPN) and injects a nulling current into the signal path. The integration time constant of the offset nulling loop is set by capacitor COFS from IOFS (QOFS) to VCMO. This forms a high-pass response for the baseband signal path with a lower 3dB frequency of
f pass =
1 2 200 COFS
Alternatively, the user can externally adjust the DC offset by driving IOFS (QOFS) with a digital-to-analog converter or other voltage source. In this case, the baseband circuit will operate all the way down to DC (fpass=0Hz). The integrator output current is only 50uA and can be easily overridden with an external voltage source. The IOFS (QOFS) pin must be either connected to a bypass capacitor (>0.1uF) or an external voltage source to prevent the feedback loop from oscillating.
Rev. PrF
2/11/03
-7-
AD8348
Applications
PRELIMINARY TECHNICAL DATA
Basic Connections The basic connections described here refer to the AD8348 evaluation board. The schematic for the evaluation board is shown in Figure 1. Power Supply The voltage supply for the AD8348, between 2.7V and 5V, should be connected to the +Vs test point and ground should be connected to one of the GND test points. Device Enable To enable the device, the pin ENBL should be driven to +Vs. Grounding the same pin will disable the device. On the evaluation board this can be achieved by moving SW11 to the ENBL and DENBL positions respectively. VGA Enable The VGA can be enabled by driving the voltage on the pin ENVG to +Vs. In this mode, the MX inputs are disabled and the IF inputs should be utilized. Grounding the pin will disable the VGA and the IF inputs. When the VGA is disabled the MX inputs should be used. On the evaluation board, SW12 should be positioned in either the IF or MX positions. Gain Control When the VGA is enabled, the gain can be controlled by the voltage on pin VGIN. The gain control voltage range is between 0.2 V and 1.2 V. This corresponds to a gain range between 25.6 dB and -18.3 dB. For convenience, a potentiometer R15 is provided to allow for changes in gain without the need for an additional DC voltage source. To use the potentiometer, the switch SW13 must be set to the POT position. Alternatively, an external voltage applied to either the testpoint or SMA connector labeled VGIN can set the gain. SW13 must be set to the EXT position when an external gain control voltage is used.
LO Input The local oscillator signal should be fed to the SMA connector J21. This port is terminated in 50 Ohms. The recommended LO drive level is between -10 and 0 dBm. The LO frequency at the input to the device should be twice that of the desired LO frequency at the mixer core. The applied LO frequency range is between 100 MHz and 2 GHz. IF Input The IF input should be fed into the SMA connector IFIP. The VGA must be enabled when this port is used (SW12 in the IF position). MX Input The input to the mixer input can be either single-ended or differential. The evaluation board is, by default, set for single-ended MX drive. To change to a differential drive, T41 should be removed along with resistor R42. DC blocking capacitors (C42, C43) should be installed in place of T41. This will present a nominal differential impedance of 200 Ohms (100 Ohms each side). The differential inputs should then be fed into SMA connectors MXIP and MXIN. Baseband Outputs The baseband outputs are at the IOPP, IOPN, QOPP and QOPN testpoints and SMA connectors. These outputs are not designed to drive 50 Ohm loads directly and should be presented with loads of at least 2k Ohms. Output DC Bias Level The DC bias level of the baseband amplifier outputs are by default tied to Vref through LK11. If desired, the DC bias level can be changed by removing LK11 and driving a DC voltage onto either the VCMO testpoint.
-8-
Rev. PrF
2/11/03
PRELIMINARY TECHNICAL DATA
AD8348
Evaluation Board
Figure 1 shows the schematic for the AD8348 evaluation board. Note that uninstalled components are indicated with the "OPEN" designation. The board is powered by a single supply in the range of 2.7 to 5.5 V. Table I details the various configuration options of the evaluation board.
Figure 1. Evaluation board schematic.
Rev. PrF
2/11/03
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AD8348
PRELIMINARY TECHNICAL DATA
Figure 2. Evaluation Board Top Layer.
Figure 3. Evaluation Board Top Silkscreen.
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Rev. PrF
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PRELIMINARY TECHNICAL DATA
AD8348
Figure 4. Evaluation Board Bottom Layer.
Figure 5. Evaluation Board Bottom Silkscreen.
Rev. PrF
2/11/03
- 11 -
AD8348
Component +Vs, GND SW11, ENBL
PRELIMINARY TECHNICAL DATA
Table I Evaluation Board Configuration Options
Function Power Supply and Ground Vector Pins Device Enable: Place SW11 in the ENBL position to connect the ENBL pin to +Vs. Place in the DENBL position to disable the device by grounding the pin ENBL through a 50 Ohm pull down resistor. The device may also be enabled via an external voltage applied to ENBL or VENB. Gain Control Selection: With SW13 in the POT position the gain of the VGA can be set using the potentiometer R15. With SW13 in the EXT position the VGA gain can be set by an external voltage to SMA connector VGIN. For VGA operation the VGA must first be enabled by setting SW12 to the IF position. VGA Enable Selection: With SW12 in the IF position, the ENVG pin is connected to +Vs and the VGA is enabled. The IF input should be used when SW12 is in the IF position. With SW12 in the MX position the ENVG pin is grounded and the VGA is disabled. The MX inputs should be used when SW12 is in the MX position. IF Input: The single-ended IF signal should be connected to this SMA connector. R31 and R32 form a L-pad that presents a 50 Ohm termination to the input. Mixer Inputs: These inputs can be configured for either differential or single-ended operation. The default is single-ended operation with T41 and R42 installed. In single-ended mode the input is applied to the 50 Ohm SMA connector MXIP. For differential drive, T41 should be removed along with resistor R42. DC blocking capacitors (C42, C43) should be installed in place of T41. This will present a nominal differential impedance of 200 Ohms (100 Ohms each side). The differential inputs should then be fed into SMA connectors MXIP and MXIN. Baseband Amplifier Output Bias: Installing LK11 connects VREF to VCMO. This sets the bias level on the baseband amplifiers to VREF which is equal to approximately 1V. Alternatively, with LK11 removed, the bias level of the baseband amplifiers can be set by applying an external voltage to the VCMO testpoint. Baseband Amplifier Outputs and Output Filter: Additional low-pass filtering can be provided at the baseband output with these filters. Mixer Output DC Blocking Capacitors: The mixer outputs are biased to VCMO. To prevent damage to test equipment that cannot tolerate DC biases, C10 is provided to block the DC component, thus protecting the test equipment. Baseband Filter: These components are provided for baseband filtering between the mixer outputs and the baseband amplifier inputs. The baseband amplifier input impedance is high and the filter termination impedance is set by R2. See Table II below for jumper settings. Offset Compensation Loop Disable: Installing these jumpers will disable the offset compensation loop for the corresponding channel. Default Condition Not Applicable SW11 = ENBL
SW13, R15, VGIN
SW2 = POT
SW12
SW12 = IF
IFIP, R31, R32 MXIP, MXIN T41, R42 C42, C43
R31 = 57.6 Ohms R32 = 174 Ohms T41 = ETC4-1-2 R42 = 0 Ohms
LK11, VCMO
LK11 Installed
C8, C9, R4, R5 (I and Q) C10 (I and Q)
R4, R5 = 0 Ohms C10 = 0 Ohms
C1 - C7 R1, R2 L1 - L3 (I and Q) LK5 (I and Q)
All = OPEN
LK5x = OPEN
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PRELIMINARY TECHNICAL DATA
AD8348
Table II Filter Jumper Configuration Options
Condition xMXO to xAIN direct xMXO to xAIN via filter xMXO to J1x direct, xAIN unused xMXO to J1x via filter, xAIN unused Drive xAIN from J1x
(x = I and Q)
LK1 x * *
LK2 x * *
LK3 x * *
LK4 x
* * *
OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead TSSOP (RU-28)
0.386 (9.80) 0.378 (9.60)
28
15
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 14
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 deg 0 deg
0.028 (0.70) 0.020 (0.50)
Rev. PrF
2/11/03
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